Organized many of the test support to jpegenc/testing.  Also
adding models and model tests.

This commit contains the addition of general processing element
models (ProcessingSubblock).  This commit also has some other
minor changes made during test creation.

Added a DCT data flow test to emulate the possible data flow through
the system.  This commit also has changed to the interfaces, the
previous simulation `assign` functions were replaced with the `next`
attribute.  The `assign` function is now a myhdl.block to be used
in the convertible HDL blocks.

The Verilog cosimulation tests, reference design tests, were moved
to a separate directory.  This was done to organize the tests.  The
cosim (ref tests) being in a separate directory can be troublesome.
The cosim needs to know the path to the Verilog files and the VPI
module.  When run from pytest this typically will be from the
test_jpeg/tests/ directory, all the paths would be relative from
here.  Currently all the paths are fixed from the tests/ dir, this
should be enhanced in the future to determine which directory the
pytest runner exectuing from and adjust the paths accordingly.